A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes

A sensitivity analysis is used to compute an analytical expression for the propagation delay of an emitter-coupled logic (ECL) gate in terms of the electrical parameters of the circuit. These electrical parameters are in turn related to the processing parameters through approximate analytical equations and computer simulation programs. In this way, a simple means is evolved of optimizing an ECL process for maximum circuit speed. The accuracy of the propagation-delay expression and the related equations for the electrical parameters are verified by comparison with experimental results on 6- mu m geometry circuits. By means of the propagation-delay expression, it is shown that the optimum propagation delay at 6- mu m geometry is 320 ps for a conventional process and 160 ps for a self-aligned process. On scaling to a geometry of 0.5 mu m, a propagation delay of 20 ps is predicted for a fully optimized self-aligned process.<>