Pentalevel Resist Process for the Precise Fabrication of Small Area SIS Junctions

Author

Lichtenberger, Arthur Weston ; Stronko, Gregory S. ; Wang, Jie ; Cecil, Thomas W. ; Zhang, Jian Z.

Author_Institution

Charles L. Brown Dept. of Electr. & Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA

Volume

19

Issue

3

fYear

2009

fDate

6/1/2009 12:00:00 AM

Firstpage

222

Lastpage

225

Abstract

We have fabricated high quality M1/barrier/M2/Au superconducting insulating superconducting (SIS) junctions with Au over-layers using a new multilayer pentalevel resist process. The wafer/NFR/polyimide/SiO₂/Cr/imaging-resist pentalevel structure enables precise definition of submicron junction features in a self-aligned insulation process. This scheme, unlike our previous multilevel resists, affords precise definition of the final Nb layer from an initial etch of a thinner top Cr layer. The Cr layer, defined with chlorine based RIE, serves as an excellent mask for the subsequent fluorine and oxygen based RIE etches of the remaining pentalevel stack and M2 electrode. We present a detailed description of the pentalevel process and electrical characteristics of NbTiN SIS junctions fabricated with this new technique.

Keywords

gold; masks; sputter etching; superconducting junction devices; Au; M1/barrier/M2/Au superconducting insulating superconducting junctions; M2 electrode; RIE etches; mask; multilayer pentalevel resist process; self-aligned insulation process; Liftoff; SIS; multilayer; resist; self-aligned;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/TASC.2009.2019282

Filename

5089408