Switching conditions for CMOS latch-up path with shunt resistances

Analytical expressions for the switching points of a one-dimensional p-n-p-n representation for a CMOS latch-up path are obtained without the traditional simplifying assumptions. A new criterion for the holding current is established. The results are applicable to the general case where the emitting junctions are shunted by resistances, as well as the simple p-n-p-n structure. The "holding current" of the path is discussed in some detail and predicted values are compared to those obtained experimentally.