Title :
Four-quadrant CMOS analogue multiplier
Author :
Kim, You Ho ; Park, S.B.
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
3/26/1992 12:00:00 AM
Abstract :
A new four-quadrant CMOS analogue multiplier is presented which is based on the operation of MOS transistors in the saturation region and has simple circuit configuration and good linearity. The simulation result shows that less than 1% distortion can be obtained for input signals of 5.6 V peak to peak and supply voltages of +or-5 V.
Keywords :
CMOS integrated circuits; analogue computer circuits; linear integrated circuits; multiplying circuits; 5 V; 5.6 V; CMOS; MOS transistors; analogue multiplier; circuit configuration; distortion; four quadrant multiplier; linearity; operation; saturation region; signal voltage; simulation result; supply voltages;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19920410
