Title :
14.9 ps/2.2 mW charge-buffered active-pull-down ECL circuit
Author :
Chin, Kwan-Wu ; Chuang, Ching-Te ; Warnock, J.D.
Author_Institution :
IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
3/26/1992 12:00:00 AM
Abstract :
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0.8 mu m double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9 ps/2.2 mW, 20.7 ps/1.2 mW, and 24.5 ps/0.77 mW have been achieved.
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; 0.8 micron; 14.9 to 24.5 ps; 2.2 to 0.77 mW; ECL circuit; charge-buffered active-pull-down; double-poly; emitter-follower stage; gate delays; gate propagation delay; power consumption reduction; selfaligned bipolar process; trench-isolated;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19920421
