DocumentCode
1089979
Title
Dynamically rule-programmable VLSI processor for fully-parallel inference
Author
Hanyu, Takahiro ; Takeda, Kenji ; Higuchi, Tatsuro
Author_Institution
Tohoku Univ., Sendai, Japan
Volume
28
Issue
7
fYear
1992
fDate
3/26/1992 12:00:00 AM
Firstpage
695
Lastpage
697
Abstract
A dynamically rule-programmable fully-parallel inference accelerator VLSI is proposed for real-time rule-based systems with large databases. The direct multiple-valued encoding of each attribute value in rules and the threshold voltage programming of floating-gate MOS devices make a high-performance VLSI possible. The improvement of performance compared with the conventional binary implementation is demonstrated.
Keywords
MOS integrated circuits; VLSI; deductive databases; inference mechanisms; knowledge based systems; logic programming; microprocessor chips; parallel architectures; parallel programming; real-time systems; IKBS; VLSI processor; direct multiple-valued encoding; dynamically rule-programmable; floating-gate MOS devices; fully-parallel inference; inference accelerator; large databases; real-time rule-based systems; threshold voltage programming;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19920439
Filename
133076
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