• DocumentCode
    1090093
  • Title

    Multiplierless fast Fourier transform architecture

  • Author

    Jiang, M. ; Yang, B. ; Huang, R. ; Zhang, T.Y. ; Wang, Y.Y.

  • Author_Institution
    Inst. of Microelectron., Peking Univ., Beijing
  • Volume
    43
  • Issue
    3
  • fYear
    2007
  • Firstpage
    191
  • Lastpage
    192
  • Abstract
    A multiplierless processor architecture is proposed for hardware implementation of fast Fourier transform. Distributed arithmetic is applied to simplify expensive butterfly operations and twiddle multiplications. The novel architecture can largely reduce area cost by replacing complex multipliers and adders with DA lookup tables. Both 8-bit and 16-bit 64-point FFT processors were designed, and the synthesis result shows the designs can attain much lower area cost while keeping real-time processing speed
  • Keywords
    coprocessors; distributed arithmetic; fast Fourier transforms; table lookup; 16 bit; 8 bit; distributed arithmetic; fast Fourier transform; lookup tables; multiplier-less processor architecture;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • Filename
    4087810
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1090093