DocumentCode
1090481
Title
Hardware modifications in radix-2 cascade FFT processors
Author
Agrawal, J.P. ; Ninan, Jacob
Author_Institution
Indian Institute of technology, Madras, India
Volume
26
Issue
2
fYear
1978
fDate
4/1/1978 12:00:00 AM
Firstpage
171
Lastpage
172
Abstract
In this correspondence, some techniques are presented, which reduce coefficient storage and hardware cost of cascade FFT processors. Computer simulation results are presented which give hardware-error tradeoffs and also show the effect of coefficient accuracy. A reduced hardware multiplier is suggested which gives only insignificant loss in accuracy.
Keywords
Computational modeling; Computer errors; Computer simulation; Costs; Digital arithmetic; Frequency; Hardware; Jacobian matrices; Samarium; Signal processing;
fLanguage
English
Journal_Title
Acoustics, Speech and Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
0096-3518
Type
jour
DOI
10.1109/TASSP.1978.1163061
Filename
1163061
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