Fabrication and Low Temperature Characterization of Ge (110) and (100) p-MOSFETs

Author

I-Hsieh Wong ; Yen-Ting Chen ; Jhih-Yang Yan ; Huang-Jhih Ciou ; Yu-Sheng Chen ; Chee Wee Liu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

61

Issue

6

fYear

2014

fDate

Jun-14

Firstpage

2215

Lastpage

2219

Abstract

The Ge p-MOSFETs on (110) substrates using two-step implantation and NiGe contacts have been demonstrated. The record peak mobility of 528 cm²/V·s of the (110) Ge device is measured by the spilt C-V method and can be further enhanced by proper stress. Ge p-FETs on (110) substrates have lower mobility enhancement than (100) devices under compressive strain along the channel. The peak mobility decreases with decreasing temperature due to impurity scattering. The larger density of interface states causes the larger threshold voltage shift from the room temperature to 100 K as compared with Si MOSFETs.

Keywords

MOSFET; elemental semiconductors; germanium; hole mobility; impurity scattering; interface states; Ge; compressive strain; impurity scattering; interface states; low temperature characterization; mobility enhancement; p-MOSFET; record peak mobility; two step implantation; Logic gates; MOSFET; MOSFET circuits; Resistance; Silicon; Strain; Substrates; Ge; mobility enhancement; strain; temperature dependence of threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2014.2318083

Filename

6817678