Supply-Noise Interactions Among Submodules Inside a Charge-Pump PLL

Behavioral models are necessary to shorten the design turn-around time of phase-locked loops (PLLs). For general cases in a system-on-chip, the PLL can resist the supply noise from other modules by a low-dropout regulator. Therefore, interactions among the supply ports of PLL submodules play a much more important part in the overall noise performance. In this brief, we propose a time-domain charge-pump PLL model including supply-noise interactions inside PLL. Described by Verilog-A, the behavioral results are compared with the simulated results of transistor circuits. It can be seen that the proposed model has reduced the simulation time to about 1.7% when compared with transistor-level simulating by SpectreRF. Under a nonideal power grid, our model can improve the jitter simulation accuracy when compared with the conventional model, e.g., simulated jitter error is lowered by 52.6% under a power grid with 8-Ω power-line segment and 1-pF decoupling capacitance.