• DocumentCode
    1091324
  • Title

    Automated gate array scaling

  • Author

    Akers, L.A.

  • Volume
    31
  • Issue
    2
  • fYear
    1984
  • fDate
    2/1/1984 12:00:00 AM
  • Firstpage
    157
  • Lastpage
    159
  • Abstract
    A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59 percent and the speed was increased more than 40 percent is illustrated.
  • Keywords
    Algorithm design and analysis; Integrated circuit manufacture; Integrated circuit technology; Interpolation; Logic; Resistors; Virtual reality;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1984.21493
  • Filename
    1483778
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1091324