• DocumentCode
    1091368
  • Title

    A three-dimensional CMOS design methodology

  • Author

    Hoefflinger, Bernd ; Liu, Sie T. ; Vajdic, Branislav

  • Author_Institution
    Purdue University, West Lafayette, IN
  • Volume
    31
  • Issue
    2
  • fYear
    1984
  • fDate
    2/1/1984 12:00:00 AM
  • Firstpage
    171
  • Lastpage
    173
  • Abstract
    A technology-updatable design methodology for three-dimensional (3-D) CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: 1) technology level, 2) mask level, 3) transistor level, and 4) logic level. A novel transistor level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples is presented.
  • Keywords
    CMOS logic circuits; CMOS technology; Design methodology; Insulation; Inverters; Isolation technology; Logic devices; Silicon on insulator technology; Surfaces; Thin film transistors;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1984.21496
  • Filename
    1483781
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1091368