Title :
A three-dimensional CMOS design methodology
Author :
Hoefflinger, Bernd ; Liu, Sie T. ; Vajdic, Branislav
Author_Institution :
Purdue University, West Lafayette, IN
fDate :
2/1/1984 12:00:00 AM
Abstract :
A technology-updatable design methodology for three-dimensional (3-D) CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: 1) technology level, 2) mask level, 3) transistor level, and 4) logic level. A novel transistor level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples is presented.
Keywords :
CMOS logic circuits; CMOS technology; Design methodology; Insulation; Inverters; Isolation technology; Logic devices; Silicon on insulator technology; Surfaces; Thin film transistors;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1984.21496
