Title :
Design methodology of a 1.2-µm double-level-metal CMOS technology
Author :
Preckshot, Nancy E. ; Campbell, Stephen A. ; Heikkila, Walter W. ; Dokos, Dimitri ; Passow, Robin H. ; Grant, Wesley N. ; Schultz, Dale ; Victorey, John P.
Author_Institution :
Sperry Semiconductor Operations, Eagan, MN
fDate :
2/1/1984 12:00:00 AM
Abstract :
An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-µm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.
Keywords :
CMOS process; CMOS technology; Circuits; Delay; Design methodology; Etching; Implants; Libraries; Resists; Very large scale integration;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1984.21504
