Minimum test chip sample size selection for characterizing process parameters

A method for determining a test chip sample size to estimate effectively the electrical parameter distributions on an integrated circuit wafer is presented. This method gives relations among sample size and the figure of merit for four statistical techniques (trimmed mean, biweighted mean, median, and arithmetic mean) by which estimates are calculated. To demonstrate its use, the method has been applied to the evaluation of a CMOS fabrication process. Measurements on wafers completely patterned with identical test chips were used to determine actual parameter distributions for an entire wafer (true parameter values). Estimates of true parameters were determined using a site selection plan which is representative of sampling plans employed in industry. The above four statistical techniques were used to compute estimates for electrical parameters and their respective figures of merit. These estimates were compared with the true parameter values determined from testing all test chips on the wafer. This method may be used in conjunction with other criteria for determining test chip sample size and enables one to make judgments on the effectiveness of sampling strategies for various processes and process technologies. The results, reported in this paper for CMOS processes, are interpreted using graphs of the figure of merit versus the sample size.