DocumentCode
1091716
Title
Evidence of two-dimensional carrier confinement in thin n-channel SOI gate-all-around (GAA) devices
Author
Colinge, J.P. ; Baie, X. ; Bayot, V.
Author_Institution
UCL-Maxwell-DICE, Louvain-la-Neuve, Belgium
Volume
15
Issue
6
fYear
1994
fDate
6/1/1994 12:00:00 AM
Firstpage
193
Lastpage
195
Abstract
The effect of two-dimensional electron confinement is observed in thin-film, gate-all-around SOI transistors operated at low temperature. Physical 3D confinement in a thin silicon film using the silicon/gate oxide potential barrier (in contrast to heterojunction or electrostatic confinement) is shown for the first time. In these devices volume inversion gives rise to a 2DEG, and the population of the energy subbands can be controlled by the gate voltage. The position of transconductance peaks and valleys, corresponding to the population of different subbands as the gate voltage is increased, is in good agreement with theoretical predictions.<>
Keywords
insulated gate field effect transistors; semiconductor-insulator boundaries; silicon; thin film transistors; two-dimensional electron gas; 2DEG; Si-SiO/sub 2/; Si/gate oxide potential barrier; gate-all-around devices; low temperature operation; thin n-channel SOI devices; two-dimensional carrier confinement; volume inversion; Carrier confinement; Electrons; Electrostatics; Heterojunctions; Semiconductor films; Silicon; Temperature; Thin film transistors; Transconductance; Voltage control;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.286689
Filename
286689
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