• DocumentCode
    1091811
  • Title

    Programming models for hybrid FPGA-cpu computational components: a missing link

  • Author

    Andrews, David ; Niehaus, Douglas ; Jidin, Razali ; Finley, Michael ; Peck, Wesley ; Frisbie, Michael ; Ortiz, Jorge ; Komp, Ed ; Ashenden, Peter

  • Author_Institution
    Kansas Univ., Lawrence, KS, USA
  • Volume
    24
  • Issue
    4
  • fYear
    2004
  • Firstpage
    42
  • Lastpage
    53
  • Abstract
    Emerging hybrid chips containing cpu and FPGA components are an exciting new development promising commercial off-the-shelf economies of scale, while also supporting hardware customization.
  • Keywords
    embedded systems; field programmable gate arrays; hardware-software codesign; multi-threading; reconfigurable architectures; shared memory systems; commercial off-the-shelf; embedded system; field programmable gate array; hardware customization; hardware-software codesign; hybrid FPGA-cpu computational component; programming model; reconfigurable architecture; Best practices; Computer languages; Control systems; Costs; Economies of scale; Field programmable gate arrays; Hardware; Integrated circuit modeling; Programming profession; Time to market;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2004.36
  • Filename
    1331278
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1091811