DocumentCode :
10925
Title :
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors
Author :
Sierra, R. ; Carreras, C. ; Caffarena, G. ; Lopez Bario, C.A.
Author_Institution :
Electr. Eng. Dept., Tech. Univ. of Madrid, Madrid, Spain
Volume :
34
Issue :
1
fYear :
2015
fDate :
Jan. 2015
Firstpage :
52
Lastpage :
62
Abstract :
Fixed-point arithmetic datapaths with heterogeneous scaling and wordlengths are commonplace in resource, latency, or power constrained designs. This paper describes and proves correct a formal method for accurate high-level casting of optimal adders and subtractors. The proposed approach allows for an early accurate estimation of resource usage which is then available for high-level decision-taking in the design flow. As a result, decoupling between high-level and low-level synthesis is achieved. Results concerning the impact of the approach on resource estimates and a discussion on the wide applicability of the method are presented.
Keywords :
adders; computational complexity; electronic design automation; fixed-point arithmetic datapaths; formal method; heterogeneous fixed-point adders; heterogeneous fixed-point subtractors; heterogeneous scaling; high-level decision-taking; Adders; Casting; Educational institutions; Indexes; Optimization; Quantization (signal); Vectors; Arithmetic; EDA; HLS; arithmetic; datapath; electronic design automation (EDA); fixed-point; high-level synthesis (HLS);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2014.2365094
Filename :
6936317
Link To Document :
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