Adaptive enhancement of timing accuracy and waveform quality in high-performance IC testers

A means of improving edge-placement accuracy and waveform quality in high-speed high-performance integrated circuit test and verification systems is being developed. Its aim is to minimize timing skew, maintain signal integrity at the device under test (DUT), and actively reduce waveform errors caused by uncertain DUT loading and transmission path imperfections. The path between the pin electronic card (PEC) and the DUT is modeled using a signal flow graph (SFG) technique. The model contains both lumped and distributed circuit elements, each of which is represented by scattering parameters. Frequency domain reflectometry (FDR) is used to measure voltage reflection coefficients of both the load (DUT) and PEC receiver ends of the transmission path. Load models are obtained through a direct search optimization algorithm. Examples of time domain compensation are presented for matched and mismatched transmission paths