CACTI: an enhanced cache access and cycle time model

Author

Wilton, Steven J E ; Jouppi, Norman P.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

31

Issue

5

fYear

1996

fDate

5/1/1996 12:00:00 AM

Firstpage

677

Lastpage

688

Abstract

This paper describes an analytical model for the access and cycle times of on-chip direct-mapped and set-associative caches. The inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters. The model gives estimates that are within 6% of Hspice results for the circuits we have chosen. This model extends previous models and fixes many of their major shortcomings. New features include models for the tag array, comparator, and multiplexor drivers, nonstep stage input slopes, rectangular stacking of memory subarrays, a transistor-level decoder model, column-multiplexed bitlines controlled by an additional array organizational parameter, load-dependent size transistors for wordline drivers, and output of cycle times as well as access times. Software implementing the model is available via ftp

Keywords

cache storage; content-addressable storage; integrated memory circuits; memory architecture; CACTI; access times; analytical model; bitlines; comparator; cycle times; decoder; direct-mapped caches; ftp software; multiplexor driver; on-chip memory circuits; set-associative caches; tag array; wordlines; Analytical models; Computer architecture; Costs; Councils; Decoding; Delay estimation; Driver circuits; Equations; Stacking; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.509850

Filename

509850