Power dissipation analysis and optimization of deep submicron CMOS digital circuits

Author

Gu, Richard X. ; Elmasry, Mohamed I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

31

Issue

5

fYear

1996

fDate

5/1/1996 12:00:00 AM

Firstpage

707

Lastpage

713

Abstract

This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and η, which reflects the drain induced barrier lowering, are also addressed

Keywords

CMOS digital integrated circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; leakage currents; BSIM; Berkeley Short-Channel IGFET model; HSPICE simulation; analytical model; deep submicron CMOS digital circuits; design methodology; drain induced barrier lowering; optimization; power dissipation analysis; power-delay product minimisation; standby power dissipation; supply voltage; switching power dissipation; threshold voltages; Analytical models; CMOS digital integrated circuits; Circuit simulation; Design methodology; Digital circuits; Power dissipation; Semiconductor device modeling; Switching circuits; Threshold voltage; Upper bound;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.509853

Filename

509853