Title :
On-Chip IDDQ testability schemes for detecting multiple faults in CMOS ICs
Author :
Hwang, Changku ; Ismail, Mohammed ; Degroat, Joanne E.
Author_Institution :
Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA
fDate :
5/1/1996 12:00:00 AM
Abstract :
In this paper we present two on-chip design-for-testability (DFT) schemes for CMOS ICs. One is for small circuits and the other for large circuits. Both schemes identify a faulty area on a chip with only a small area overhead for the additional circuitry and at most two extra pins. Moreover, if faults occur in different areas, multiple faults can also be detected with the proposed schemes. To demonstrate the ideas, DFT is incorporated in a 4-bit carry look ahead adder/subtractor (CLAAS) as well as a 16-bit arithmetic logic unit (ALU). Simulation results are given
Keywords :
CMOS digital integrated circuits; VLSI; built-in self test; design for testability; fault location; integrated circuit design; integrated circuit testing; logic design; logic testing; ALU; BIST; CMOS IC; arithmetic logic unit; carry look ahead adder/subtractor; design-for-testability schemes; multiple faults detection; onchip DFT schemes; onchip IDDQ testability schemes; CMOS integrated circuits; Circuit faults; Circuit optimization; Circuit testing; Electrical fault detection; Fault detection; Logic testing; MOSFET circuits; Pins; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
