A GHz MOS adaptive pipeline technique using MOS current-mode logic

Author

Mizuno, Masayuki ; Yamashina, Masakazu ; Furuta, Koichiro ; Igura, Hiroyuki ; Abiko, Hitoshi ; Okabe, Kazuhiro ; Ono, Atsuki ; Yamada, Hachiro

Author_Institution

Microelectron. Res. Labs., NEC Corp., Kanagawa, Japan

Volume

31

Issue

6

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

784

Lastpage

791

Abstract

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-μm MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits

Keywords

MOS logic circuits; adders; current-mode logic; pipeline processing; 0.4 micron; 1 GHz; 1.6 V; 64 bit; MCML circuit; MOS current-mode logic; adaptive pipeline; clock skew; compensation; device-parameter deviations; double-stage pipeline adder; jitter; low-noise variable delay circuit; operating-environment variations; power dissipation; propagation delay time; Adders; CMOS logic circuits; Clocks; Frequency; Logic circuits; Logic devices; Pipelines; Power dissipation; Propagation delay; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.509864

Filename

509864