A 1.2 GFLOPS neural network chip for high-speed neural network servers

Author

Kondo, Yoshikazu ; Koshiba, Yuichi ; Arima, Yutaka ; Murasaki, Mitsuhiro ; Yamada, Tuyoshi ; Amishiro, Hiroyuki ; Mori, Hakuro ; Kyuma, Kazuo

Author_Institution

Semicond. Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

31

Issue

6

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

860

Lastpage

864

Abstract

This paper describes a digital neural network chip for high-speed neural network servers. The chip employs single-instruction multiple-data stream (SIMD) architecture consisting of 12 floating-point processing units, a control unit, and a nonlinear function unit. At a 50 MHz clock frequency, the chip achieves a peak speed performance of 1.2 GFLOPS using 24-bit floating-point representation. Two schemes of expanding the network size enable neural tasks requiring over 1 million synapses to be executed. The average speed performances of typical neural network models are also discussed

Keywords

CMOS digital integrated circuits; floating point arithmetic; network servers; neural chips; parallel architectures; real-time systems; 1.2 GFLOPS; 24 bit; 50 MHz; average speed performances; floating-point processing units; floating-point representation; high-speed neural network servers; network size; neural network chip; nonlinear function unit; peak speed performance; single-instruction multiple-data stream; Backpropagation; Clocks; Digital signal processing chips; Dynamic range; Frequency; Laboratories; Network servers; Neural networks; Neurons; Process control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.509875

Filename

509875