Title :
Multiple-valued pads for binary chips
Author :
Costa, A.J. ; Valencia, Manuel ; Barriga, Angel ; Huertas, Jose Luis ; Bellido, M.J.
Author_Institution :
Dpto. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectron., Edificio CICA, Sevilla, Spain
fDate :
4/9/1992 12:00:00 AM
Abstract :
A family of CMOS multiple-valued (MV) pads is presented. The most prominent advantage of these pads is the area gain (40-50%) if they are compared with the corresponding binary pads. Other features are low power consumption and high fanout. This family can be used in chips with very high pinout requirements, decreasing the complexity of the interconnections at board level.
Keywords :
CMOS integrated circuits; VLSI; integrated logic circuits; many-valued logics; CMOS; area gain; binary chips; board level; complexity; fanout; interconnections; low power consumption; multiple-valued pads; pinout requirements;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19920501
