Substrate resistance calculation for latchup modeling

The input and output circuits are the main triggering mechanisms of latchup in CMOS technology. We have studied the triggering capability of these circuits and the effectiveness of using guard rings to suppress triggering. We present a method to estimate the substrate potential induced by a triggering current in these circuits and the effect of using guard rings to prevent latchup. It was necessary to include effects of the field-threshold implant to obtain good agreement between theory and measurements.