DocumentCode :
1093447
Title :
ARB: a hardware mechanism for dynamic reordering of memory references
Author :
Franklin, Manoj ; Sohi, Gurindar S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
Volume :
45
Issue :
5
fYear :
1996
fDate :
5/1/1996 12:00:00 AM
Firstpage :
552
Lastpage :
571
Abstract :
To exploit instruction level parallelism, it is important not only to execute multiple memory references per cycle, but also to reorder memory references-especially to execute loads before stores that precede them in the sequential instruction stream. To guarantee correctness of execution in such situations, memory reference addresses have to be disambiguated. This paper presents a novel hardware mechanism, called an Address Resolution Buffer (ARB), for performing dynamic reordering of memory references. The ARB supports the following features: (1) dynamic memory disambiguation in a decentralized manner, (2) multiple memory references per cycle, (3) out-of-order execution of memory references, (4) unresolved loads and stores, (5) speculative loads and stores, and (6) memory renaming. The paper presents the results of a simulation study that we conducted to verify the efficacy of the ARB for a superscalar processor. The paper also shows the ARB´s application in a multiscalar processor
Keywords :
buffer storage; processor scheduling; storage management; ARB; Address Resolution Buffer; dynamic reordering; dynamic scheduling; hardware mechanism; instruction level parallelism; memory address disambiguation; multiscalar processor; reorder memory references; speculative execution; superscalar processor; unresolved memory references; Dynamic scheduling; Hardware; Out of order; Processor scheduling; Read-write memory;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.509907
Filename :
509907
Link To Document :
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