DocumentCode
1093490
Title
Automated technique for high-level circuit synthesis from temporal logic specifications
Author
Dowsing, R. ; Elliott, R. ; Marshall, I.
Author_Institution
Sch. of Inf. Syst., East Anglia Univ., Norwich, UK
Volume
141
Issue
3
fYear
1994
fDate
5/1/1994 12:00:00 AM
Firstpage
145
Lastpage
152
Abstract
A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined
Keywords
circuit CAD; digital circuits; formal specification; specification languages; temporal logic; AST; Tempura; digital circuit synthesis; error-encoder circuit; general-purpose strategy; high-level behavioural specifications; high-level circuit synthesis; synthesis tool; temporal logic specifications; temporal-logic language;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings -
Publisher
iet
ISSN
1350-2387
Type
jour
DOI
10.1049/ip-cdt:19941005
Filename
287056
Link To Document