DocumentCode :
109356
Title :
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation
Author :
Shen-Fu Hsiao ; Po-Han Wu ; Chia-Sheng Wen ; Meher, Pramod Kumar
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
Volume :
62
Issue :
5
fYear :
2015
fDate :
May-15
Firstpage :
466
Lastpage :
470
Abstract :
Table-lookup-and-addition methods provide multiplierless function evaluation using multiple lookup tables and a multioperand adder. In spite of their high-speed operation, they are only practical in low-precision applications due to the fast increase in table size with precision width. In this brief, we present two methods for table size reduction by decomposing the original table of initial values into two or three tables with fewer entries and/or smaller bit width. The proposed table decompositions do not incur any extra rounding errors so that the original table can be completely recovered. Experimental results demonstrate significant saving of table sizes compared with the best of the prior designs of the multipartite methods.
Keywords :
adders; graph theory; performance evaluation; table lookup; lookup-table-based multiplierless function evaluation; multioperand adder; multipartite method; precision width; table decomposition; table size; table size reduction method; table-lookup-and-addition methods; Accuracy; Adders; Approximation methods; Indexes; Silicon compounds; Table lookup; Bipartite; Computer Arithmetic; Function Evaluation; Multipartite; Table-Based Design; computer arithmetic; function evaluation; multipartite; table-based design;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2014.2386232
Filename :
6998028
Link To Document :
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