Advanced DMOS memory cell using a new isolation structure

Advanced DMOS memory cell structure, which employs a combination of n⁺buried layer and trench isolation, is proposed. This structure provides a narrower isolation width (∼1.5 µm), about 4 times hold time improvement, higher alpha-particle immunity, and easier p-well design. The alpha-flux acceleration experiment shows that the reflecting potential barrier between n⁺buried layer and n-substrate reduces the number of diffusing holes from the substrate to about one tenth. A new writing method, which employs capacitance coupling between bit line and charge storage region, is also described. Adopting this writing method, the DMOS cell size can be reduced 20 percent.