Title :
VLSI architecture for sparse matrix multiplication
Author_Institution :
Dept. of Electron. & Electr. Eng., Sheffield Univ.
fDate :
5/9/1996 12:00:00 AM
Abstract :
A new VLSI architecture for sparse matrices reduces the I/O and reduces the number of trivial multiplications. A two pipeline 30 MHz processor has been fabricated. This device performs 60 million MACs per second and reduces the time complexity for matrix multiplication by several orders of magnitude for most applications
Keywords :
VLSI; computational complexity; matrix multiplication; pipeline arithmetic; sparse matrices; 30 MHz; MACs; VLSI architecture; sparse matrix multiplication; time complexity; trivial multiplications; two pipeline processor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960606
