DocumentCode
1093958
Title
Case study and efficient modelling for variational chemical-mechanical planarisation
Author
Zhang, X. ; He, L. ; Gerousis, V. ; Song, L. ; Teng, C.-C.
Author_Institution
Univ. of California Los Angles, Los Angeles, CA
Volume
2
Issue
1
fYear
2008
fDate
2/1/2008 12:00:00 AM
Firstpage
30
Lastpage
36
Abstract
Chemical-mechanical planarisation (CMP) is an enabling technique to achieve wafer planarity in backend manufacturing processes of integrated circuits. However, CMP also causes variations in metal and dielectric thicknesses because of the non-uniformity of metal feature density. The authors first conducted a case study of CMP-induced variations using an industrial CMP simulator together with a widely used microprocessor hardcore fabricated in a 90 nm technology with eight metal layers and a system-on-chip design fabricated in a 65 nm technology with four metal layers. They revealed a few interesting characteristics on thickness variations and, particularly, vertical and horizontal correlations between variations, although such correlations have been virtually ignored by the existing study on layout optimisation. These characteristics may lead to better modelling and design optimisation for CMP variations. As an example, the authors then proposed a stochastic CMP model to efficiently incorporate CMP variations estimation in the design flow and developed two algorithms to reduce the CMP simulation runs by 7x and 3x , respectively, when compared with generating the stochastic CMP model by detailed CMP simulations.
Keywords
chemical mechanical polishing; microprocessor chips; planarisation; system-on-chip; dielectric thicknesses; integrated circuits; manufacturing processes; metal feature density; microprocessors; stochastic model; system-on-chip design fabrication; variational chemical-mechanical planarisation; wafer planarity;
fLanguage
English
Journal_Title
Circuits, Devices & Systems, IET
Publisher
iet
ISSN
1751-858X
Type
jour
DOI
10.1049/iet-cds:20070187
Filename
4464139
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