Supporting cost-effective innovation

In the nanoscale regime, speed and density of semiconductor technology continue to increase. However, skyrocketing design costs for developing gigascale system chips have slowed the creation of new design projects. Moreover, existing design and test solutions have not addressed increasing variability and reliability concerns. Variability can stem from noise, process variations, thermal effects, and power-related issues. Among these, power-induced variations can wreak havoc on performance verification and delay testing. This issue of D&T examines recent progress in dealing with noise and variations caused by IR-drop and power supply noise effects.