Analysis of soft breakdown failure with ESD on output buffer nMOSFETs and its improvement

Author

Kurachi, Ikuo ; Fukuda, Yasuhiro ; Miura, Naoki ; Ichikawa, Fumio

Author_Institution

Oki Electr. Ind. Co. Ltd., Tokyo, Japan

Volume

30

Issue

2

fYear

1994

Firstpage

358

Lastpage

364

Abstract

The leakage increase of the off-state MOSFETs after an ESD event has been studied for output transistors with the thin gate oxide and LDD structures. Leakage increase called “soft breakdown” has been found at relatively low ESD testing voltages (200-300 V). This soft breakdown is caused by the creation of interface traps due to the snap-back stressing during the ESD event. The creation of interface traps has enhanced the interface trap to band tunneling current at the drain side of the MOSFETs. The improvement of the ESD threshold has also been proposed with an additional arsenic implantation into the n^$region. It has been confirmed that the arsenic implantation improved the HBM ESD threshold to more than 2000 V

Keywords

electrostatic discharge; failure analysis; insulated gate field effect transistors; semiconductor device testing; 200 to 300 V; ESD; ESD threshold; LDD structure; arsenic implantation; band tunneling current; electrostatic discharge; interface traps; lightly doped drain structure; off-state MOSFET; output buffer nMOSFET; output transistors; snap-back stressing; soft breakdown failure; thin gate oxide structure; Circuit testing; Electric breakdown; Electron traps; Electrostatic discharge; Failure analysis; Immune system; MOSFETs; Pins; Protection; Resistors;

fLanguage

English

Journal_Title

Industry Applications, IEEE Transactions on

Publisher

ieee

ISSN

0093-9994

Type

jour

DOI

10.1109/28.287523

Filename

287523