Characterization of charge accumulation and detrapping processes related to latent failure in CMOS integrated circuits

A series of measurements were performed on a variety of custom fabricated CMOS test structures to investigate the latent mode of failure due to ESD. Devices were stressed using the current injection test method and measurement of the quiescent current state was used to detect the failure thresholds. The fault sites were further isolated and the failure mechanisms studied by measuring the electrical characteristics before and after exposure to thermal stimulation and light excitation. An analysis of the oxide trapped charge was performed using measured capacitance-voltage profiles. The measurement procedure is useful in the study of electrostatic phenomena in semiconductor devices. The results further support a charge injection/trapping model for latent failures