DocumentCode
1095161
Title
FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process
Author
Zhang, Zhuqing ; Sitaraman, Suresh K. ; Wong, C.P.
Author_Institution
Eng. & Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Volume
27
Issue
1
fYear
2004
Firstpage
86
Lastpage
93
Abstract
Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.
Keywords
curing; finite element analysis; flip-chip devices; reflow soldering; reliability; temperature distribution; thermal management (packaging); thermomechanical treatment; DSC; autocatalytic reaction model; chip dimension; curing kinetics; finite-element method; finite-element modeling; flip-chip; high assembly yield; loop program; no-flow underfill package; organic substrate; packaging cost; solder interconnect; solder joint reliability; solder reflow; temperature difference; temperature distribution; thermomechanical stress; underfill curing; underfill fillet; underfill layer; Costs; Curing; Flip chip; Kinetic theory; Packaging; Semiconductor device modeling; Soldering; Temperature distribution; Thermal stresses; Thermomechanical processes; Curing kinetics; finite-element modeling; flip-chip; no-flow underfill;
fLanguage
English
Journal_Title
Electronics Packaging Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
1521-334X
Type
jour
DOI
10.1109/TEPM.2004.830505
Filename
1331579
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