Analysis of Metastability in Pipelined ADCs

Author

Hashemi, SayedMasoud ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA

Volume

49

Issue

5

fYear

2014

fDate

May-14

Firstpage

1198

Lastpage

1209

Abstract

A critical issue in the design of high-speed ADCs relates to the errors that result from comparator metastability. Studied for flash architectures in the past, this phenomenon assumes new dimensions in pipelined converters, creating far more complex error mechanisms. This paper presents a comprehensive analysis of comparator metastability effects in pipelined ADCs and develops a method to predict the error behavior for a given input signal PDF Different error mechanisms are identified and formulated to obtain the probability of error versus the magnitude of error. An 8-bit 600 MS/s ADC fabricated in 65 nm CMOS technology has been used to assess the validity of the analytical results.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); stability; CMOS technology; analog-to-digital converters; comparator metastability effects; pipelined ADC; pipelined converters; size 65 nm; word length 8 bit; Approximation methods; Ash; Clocks; Integrated circuit modeling; Latches; Operational amplifiers; Pipeline processing; Average conductance; metastability; multi-bit stage; multiplying DAC; pipelined ADCs; sub-ADC;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2305075

Filename

6746132