• DocumentCode
    1095502
  • Title

    A bipolar population counter using wave pipelining to achieve 2.5× normal clock frequency

  • Author

    Wong, Derek C. ; De Micheli, Giovanni ; Flynn, Michael J. ; Huston, Robert E.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
  • Volume
    27
  • Issue
    5
  • fYear
    1992
  • fDate
    5/1/1992 12:00:00 AM
  • Firstpage
    745
  • Lastpage
    753
  • Abstract
    Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML (current mode logic) population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flow-through combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay
  • Keywords
    bipolar integrated circuits; combinatorial circuits; counting circuits; emitter-coupled logic; integrated logic circuits; large scale integration; pipeline processing; 250 MHz; CML; bipolar LSI chip; bipolar population counter; combinational logic; current mode logic; digital systems; wave pipelining; Algorithm design and analysis; Clocks; Combinational circuits; Counting circuits; Design automation; Frequency; Logic; Pipeline processing; Propagation delay; Registers;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.133161
  • Filename
    133161