DocumentCode
1095544
Title
Generating test patterns for VLSI circuits using a genetic algorithm
Author
Arslan, Tughrul
Volume
30
Issue
10
fYear
1994
fDate
5/12/1994 12:00:00 AM
Firstpage
778
Lastpage
779
Abstract
The authors present the development of a technique that uses genetic algorithms for the generation of rest patterns that detect single stuck-at faults in combinational VLSI circuits. As the genetic algorithm evolves, an efficient set of test patterns are produced, by searching the solution space for patterns that detect the highest number of remaining faults in the fault list
Keywords
VLSI; automatic testing; combinatorial circuits; fault location; genetic algorithms; integrated circuit testing; integrated logic circuits; logic testing; VLSI circuit testing; combinational VLSI circuits; fault list; genetic algorithm; single stuck-at faults; test pattern generation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19940524
Filename
289222
Link To Document