DocumentCode
1095665
Title
20 Gbit/s DR based timing recovery circuit
Author
Monteiro, P. ; Matos, J.N. ; Gameiro, A. ; Da Roch, J. R F
Author_Institution
Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
Volume
30
Issue
10
fYear
1994
fDate
5/12/1994 12:00:00 AM
Firstpage
799
Lastpage
800
Abstract
The design and characterisation of a 20 Gbit/s clock recovery unit developed for the RACE 2011 project of the European Community is reported. This unit is based on an open loop structure using a dielectric resonator (DR) narrowband filter. The jitter results show that the approach provides a robust and low cost solution for the clock extraction problem at very high bit rates
Keywords
dielectric resonators; digital communication systems; optical receivers; passive filters; timing circuits; 20 Gbit/s; DR based circuit; RACE 2011 project; clock extraction; clock recovery unit; dielectric resonator; high bit rates; jitter; narrowband filter; open loop structure; optical fibre links; timing recovery circuit;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19940518
Filename
289235
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