Title :
A fast VLSI adder architecture
Author :
Srinivas, H.R. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fDate :
5/1/1992 12:00:00 AM
Abstract :
An architecture for performing fixed-point, high-speed, two´s-complement, bit-parallel addition by using the carry-free property of redundant arithmetic and a fast parallel redundant-to-binary conversion scheme is presented. The internal numbers are represented in radix-2 redundant digit form, and the inputs and the output of the adder are represented in two´s-complement binary form. The adder operands are added first in a radix-2 redundant adder to produce the result in radix-2 digit (-1, 0, 1) form. This result is converted to two´s-complement binary form using the parallel conversion scheme. The high-speed conversion for long words is achieved through the use of a novel sign-select operation. The proposed adder, referred to as the sign-select conversion adder, is faster than all previous high-speed two´s-complement binary adders for large word lengths. The implementation is highly regular with repeated modules and is very well suited for VLSI implementation
Keywords :
CMOS integrated circuits; VLSI; adders; digital arithmetic; integrated logic circuits; CMOS IC; VLSI adder architecture; VLSI implementation; bit-parallel addition; carry-free property; fast adder; high-speed conversion; parallel conversion scheme; parallel redundant-to-binary conversion; radix-2 redundant digit form; redundant arithmetic; sign-select conversion adder; sign-select operation; two´s-complement binary form; Fixed-point arithmetic; Microprocessors; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of