A new VLSI architecture for full-search vector quantization

This paper presents a new systolic architecture that can be used to realize the full-search vector quantization (VQ) encoder for high-speed applications. The architecture possesses the features of regularity and modularity, and is thus very suitable for VLSI implementation. For a codebook of size N and dimension k, the VQ encoder has an area complexity of O(N), a time complexity of O(k), and I/O bandwidth of O(k). It reaches a compromise between the hardware cost and speed performance as compared to existing systolic/regular VQ encoders. At the current state of VLSI technology, the proposed system can easily be realized in a single chip for most practical applications. In addition, it provides flexibility in changing the codebook contents and extending the codebook size, where the latter is achieved simply by cascading some identical basic chips. With 0.8 μm CMOS technology to implement the proposed VQ encoder for the case of N=256, K=16, and an input data wordlength of 8 bit, the chip requires a die size of about 5.5×8.9 mm² and is able for processing 6.25 M data vectors (or 100 M data samples) every second. These features show that the proposed architecture is attractive for use in high-speed image/video applications