A 1-V operating 256-kb full-CMOS SRAM

Author

Sekiyama, Akinori ; Seki, Teruo ; Nagai, Shinji ; Iwase, Akihiro ; Suzuki, Noriyuki ; Hayasaka, Masato

Author_Institution

Fujitsu VLSI Ltd., Kasugai, Japan

Volume

27

Issue

5

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

776

Lastpage

782

Abstract

A 1-V operating 256-kb full-CMOS SRAM to be used in 1.5-V battery-based applications is presented. A reference word line and address transition detection (ATD) are used as timing control techniques to achieve adjustable timing of critical signals with a 1.5-V battery. The key circuit of the pulse sequence block is the ATD pulse generator circuit. The authors use a newly modified Schmitt trigger delay circuit. To reduce supply line noise in the chip, they needed to lower the peak of bit-line charge-up current. This was done by applying a divided word-line technique and a newly adopted staggered bit-line equalizing pulse technique. The design used a single-polysilicon and double-aluminum process with a full-CMOS memory cell of 8.5 μm×12.8 μm. The chip size is 6.0 mm×9.0 mm

Keywords

CMOS integrated circuits; SRAM chips; 1 V; 1.5 V; 1.5-V battery-based applications; 256 kbit; Al-Si; CMOS static RAM; SRAM; address transition detection; divided word-line technique; double Al process; full-CMOS memory cell; modified Schmitt trigger delay circuit; pulse generator circuit; pulse sequence block; reference word line; single polysilicon process; staggered bit-line equalizing pulse technique; timing control techniques; Batteries; CMOS technology; Circuit noise; Energy consumption; Low voltage; Noise reduction; Random access memory; SRAM chips; Stability; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.133168

Filename

133168