Fermilab physics department Fastbus TDC module

Author

Cancelo, Gustavo ; Hansen, Sten ; Cotta-Ramusino, Angelo ; Hawkey, Michael ; Patti, Robert

Author_Institution

Fermi Nat. Accel. Lab., Batavia, IL, USA

Volume

38

Issue

2

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

290

Lastpage

294

Abstract

A prototype 64-channel Fastbus TDC built at Fermilab is described. The module features a full custom CMOS four-channel gated integrator chip. One level of analog buffering at the inputs is implemented on chip. A four-event-deep output queue at the bus interface allows a high event rate with low dead time. Each channel can record up to two hits per event. With an occupation rate of 10%, the module can operate at 40000 events/s with dead time of the order of 15%. The TDC operates in common stop mode with a full scale of 1 μs and a resolution of 1 ns. Data compaction and a leading word count format have been implemented. The board is less complex than current designs

Keywords

CMOS integrated circuits; analogue-digital conversion; nuclear electronics; physics computing; CMOS four-channel gated integrator chip; Fastbus TDC module; analog buffering; bus interface; common stop mode; compaction; four-event-deep output queue; full scale; high event rate; leading word count format; low dead time; occupation rate; prototype 64-channel Fastbus TDC; resolution; Bandwidth; Connectors; Data acquisition; Energy consumption; Fastbus; Integrated circuit measurements; Laboratories; Physics; Semiconductor device measurement; Time measurement;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.289312

Filename

289312