• DocumentCode
    1096400
  • Title

    j-MOS: A versatile power field-effect transistor

  • Author

    MacIver, B.A. ; Jain, K.C.

  • Author_Institution
    General Motors Research Laboratories, Warren, MI
  • Volume
    5
  • Issue
    5
  • fYear
    1984
  • fDate
    5/1/1984 12:00:00 AM
  • Firstpage
    154
  • Lastpage
    156
  • Abstract
    A novel field-effect transistor (FET) structure that is attractive for power control applications is proposed and demonstrated. It combines MOSFET structural features and junction FET function in a simple, self-aligned structure that we refer to as j-MOS. Lateral j-MOS transistors were fabricated in silicon-on-sapphire (SOS) with on-resistance as low as 2.5 Ω in 1 cm of channel width. From this result, we project that a vertical version of j-MOS can be fabricated in silicon-on-buried insulator (SOI) with a specific on-resistance ≤ 1 m Ω.cm2, approximately a factor of two improvement over current power FET technology.
  • Keywords
    Associate members; FETs; Fabrication; MOSFET circuits; Power transistors; Silicon on insulator technology; Substrates; Testing; Thin film transistors; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1984.25867
  • Filename
    1484243
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1096400