j-MOS: A versatile power field-effect transistor

A novel field-effect transistor (FET) structure that is attractive for power control applications is proposed and demonstrated. It combines MOSFET structural features and junction FET function in a simple, self-aligned structure that we refer to as j-MOS. Lateral j-MOS transistors were fabricated in silicon-on-sapphire (SOS) with on-resistance as low as 2.5 Ω in 1 cm of channel width. From this result, we project that a vertical version of j-MOS can be fabricated in silicon-on-buried insulator (SOI) with a specific on-resistance ≤ 1 m Ω.cm², approximately a factor of two improvement over current power FET technology.