• DocumentCode
    1097097
  • Title

    Suppressing latchup in insulated gate transistors

  • Author

    Baliga, B.J. ; Adler, M.S. ; Gray, P.V. ; Love, R.P.

  • Author_Institution
    General Electric Company, Schenectady, NY
  • Volume
    5
  • Issue
    8
  • fYear
    1984
  • fDate
    8/1/1984 12:00:00 AM
  • Firstpage
    323
  • Lastpage
    325
  • Abstract
    Two-dimensional computer modeling of insulated gate transistor (IGT) structures has been used to demonstrate the suppression of latchup in the parasitic thyristor by increasing the p-base conductivity using a deep p+ diffusion in the device cells. Experimental verification of these modeling results has been performed with thyristor latching current density of over 1000 A per cm2achieved in 600-V devices at room temperature.
  • Keywords
    Current density; Electron emission; Helium; Insulated gate bipolar transistors; Insulation; MOSFETs; Semiconductor process modeling; Temperature; Thyristors; Voltage control;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1984.25932
  • Filename
    1484308
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1097097