Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS

Author

Fick, David ; Dreslinski, Ronald G. ; Giridhar, B. ; Gyouho Kim ; Sangwon Seo ; Fojtik, Matthew ; Satpathy, Sudhir ; Yoonmyung Lee ; Daeyeon Kim ; Liu, Nian ; Wieckowski, Michael ; Chen, Gang ; Mudge, Trevor ; Blaauw, D. ; Sylvester, Dennis

Author_Institution

Univ. of Michigan, Ann Arbor, MI, USA

Volume

48

Issue

1

fYear

2013

fDate

Jan. 2013

Firstpage

104

Lastpage

117

Abstract

We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with 130 nm CMOS. Measured results for a two-layer, 64-core system are discussed, with the system achieving 3930 DMIPS/W energy efficiency, which is >; 3x improvement over traditional operation at full supply voltage. This project demonstrates the feasibility of large-scale 3D design, a synergy between 3D and NTC architectures, a unique cluster-based NTC cache design, and how to maximize performance in a thermally-constrained design.

Keywords

CMOS integrated circuits; electronic engineering computing; three-dimensional integrated circuits; 3D stacking CMOS technology; ARM Cortex-M3 cores; Centip3De; cluster-based NTC architecture; large-scale 3D CMP; large-scale 3D design; near-threshold computing; size 130 nm; Clocks; Multicore processing; Random access memory; Routing; Silicon; Synchronization; Threshold voltage; 3D integrated circuits; Near-threshold computing; energy efficient; many-core architectures; through-silicon vias;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2012.2222814

Filename

6399548