A New Approach to Estimate the Effect of Single Event Transients in Complex Circuits

We describe an approach for analyzing single event transients (SETs) in complex digital circuits. The approach combines accuracy with efficiency: simulation is used for propagating the SET from the affected gate to flip-flops/latches, while hardware emulation is then used to study the resulting single or multiple-bit upset. To assess the capability of the proposed approach to deal with complex circuits, we analyzed the propagation of SETs in a microprocessor. In this paper, we analyzed the contribution to the error rate of different SET´s pulse width, as well as the impact of the workload.