Altitude SEE Test European Platform (ASTEP) and First Results in CMOS 130 nm SRAM

Author

Autran, Jean-Luc ; Roche, Philippe ; Borel, Joseph ; Sudre, Christophe ; Castellani-Coulié, Karine ; Munteanu, Daniele ; Parrassin, T. ; Gasiot, Gilles ; Schoellkopf, Jean-Pierre

Author_Institution

Inst. Univ. de France, Marseille

Volume

54

Issue

4

fYear

2007

Firstpage

1002

Lastpage

1009

Abstract

The "altitude SEE test European platform" (ASTEP) is dedicated to real-time soft-error rate (SER) testing of semiconductor memories. The platform, located in the French Alps on the "Plateau de Bure" at 2552 m, has been operational since March 2006. This test facility includes a proprietary automatic test equipment specially designed for static memory (SRAM) testing and secured remote control operation via internet. First real-time SER measurements on 3.6 Gbit of SRAMs manufactured in CMOS 130 nm technology are reported, as well as the comparison between real-time and accelerated SER. Project perspectives for CMOS 65 nm SRAMs are finally reported.

Keywords

CMOS memory circuits; SRAM chips; error analysis; materials testing; radiation effects; CMOS technology; SRAM; altitude 2552 m; altitude single event effects test European platform; remote control operation; semiconductor memories; size 130 nm; soft-error rate testing; static memory testing; Automatic control; Automatic test equipment; Automatic testing; CMOS technology; Internet; Manufacturing; Random access memory; Semiconductor device testing; Semiconductor memory; Test facilities; Accelerated tests; SER simulation; alpha-SER; atmospheric neutrons; neutron-SER; real-time testing; single-event effects (SEE); single-event rate (SER); static memory; terrestrial radiation environment;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2007.891398

Filename

4291683