Improved prediction of interface-trap generation in NMOST´s

Author

Woltjer, R. ; Paulzen, G.M.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

15

Issue

1

fYear

1994

Firstpage

4

Lastpage

6

Abstract

Hot-carrier-induced interface-trap generation in NMOSFET´s is a serious reliability hazard for CMOS circuits. Its prediction has been either inaccurate or it needed many process dependent fitting parameters. We introduce a new method that improves lifetime prediction by orders of magnitude. Our method requires no additional fitting parameter and is applicable in existing circuit simulators. From the (time dependent) voltages and currents, available in a circuit simulator, we predict the number of generated interface traps. Our prediction method has been checked in more than a hundred experiments on NMOSFET´s with 0.2-2.0-μm length, 0.8-10-μm width, and 5.5-25-nm oxide thickness.

Keywords

circuit analysis computing; electron traps; hole traps; hot carriers; insulated gate field effect transistors; interface electron states; semiconductor device models; 0.2 to 10 micron; 5.5 to 25 nm; CMOS circuits; NMOSTs; circuit simulators; hot-carrier-induced trap generation; interface trap generation; lifetime prediction; prediction method; reliability hazard; Aging; Circuit simulation; Degradation; Electron traps; Hot carriers; Integrated circuit reliability; MOSFET circuits; Prediction methods; Predictive models; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.289480

Filename

289480