DocumentCode
1098567
Title
Optimization of sidewall masked isolation process
Author
Teng, Clarence W. ; Pollack, Gordon ; Hunter, W.R.
Author_Institution
Texas Instruments, Inc., Dallas, TX
Volume
32
Issue
2
fYear
1985
fDate
2/1/1985 12:00:00 AM
Firstpage
124
Lastpage
131
Abstract
This paper presents modifications of the Sidewall Masked Isolation (SWAMI) process for VLSI device isolation which improve process reproducibility, eliminate stress induced defects, and permit flexibility in channel stop implant optimization. A novel "undercut-and-backfill" technique is introduced to eliminate a localized failure mechanism of the oxidation mask by increasing the strength of the nitride-to-nitride joint. The primary variable influencing stress-induced defect generation is the vertical length of the sidewall nitride mask as determined by the amount of recessed silicon etch prior to sidewall nitride formation. In general, a maximum length can be found below which defect-free structures can be fabricated. An optional second recessed silicon etch, following the formation of the sidewall nitride, has been developed which increases the flexibility in optimizing the channel stop implantation. Defect-free low-leakage devices with near-zero electrical channel width reduction have been obtained.
Keywords
Anisotropic magnetoresistance; Boron; Etching; Implants; Leakage current; Oxidation; Resists; Silicon; Stress; Very large scale integration;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1985.21921
Filename
1484668
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